Recently, in digital cameras or mobile phones, the amount of data handled is increasing. However, the size of the digital cameras or mobile phones is becoming smaller. To further reduce the size, many products are presented in which a DRAM (Dynamic Random Access Memory) capacitor is built within an LSI (Large Scale Integration) to reduce the chip size as a whole. Moreover, in keeping up with the LSI size reduction, the demand for increasing the operating speed of the LSI is becoming stronger.
However, increasing the operating speed of an LSI is tantamount to increasing its operating frequency. If, in case larger numbers of flipflop circuits, each operating with a clock signal, are arranged at a given site of the LSI, these numerous flipflop circuits are simultaneously run in operation, the electrical charges of power supply lines and ground interconnects flow abruptly through the flipflop circuits. The electrical charges of the power supply lines and the ground line are then decreased instantaneously to give rise to power supply voltage fluctuations.
To suppress these power supply voltage fluctuations, it has so far been proposed to provide a standard cell within an LSI. The standard cell, a gate capacitance configuration capacitor cell, operates to store the electrical charges in a gate capacitance. The gate capacitance configuration capacitor cell has both its electrodes connected to the power supply lines and the ground line to constitute a decoupling capacitor (bypass capacitor) to suppress the power supply voltage fluctuations.
However, if the gate capacitance configuration capacitor cell is arranged within the LSI, the area taken up by the LSI is increased. To suppress the LSI size from increasing, such a technique has recently been desired which allows a decoupling capacitor to be formed in the LSI without using the gate capacitance configuration capacitor cell in which electrical charges are stored in the gate capacitance.
In Patent Document 1, for example, there is disclosed a method for generating a pattern for a semiconductor integrated circuit device as a technique of forming a decoupling capacitor (bypass capacitor). The pattern generation method includes a step of designing and placing a layout pattern of a semiconductor chip including layered (stacked) interconnects of first and second interconnect layers of respective different film thicknesses. The pattern generation method also includes a step of extracting a circuit block liable to generate a noise from the layout pattern, and a step of verifying whether or not a capacitance cell may be placed on the circuit block. The pattern generation method further includes a step of placing a capacitance by sandwiching a capacitance insulation film between first and second interconnect layers in a capacitance placing region in the circuit block extracted. The capacitance placing region is a region concluded in the above verifying step to be a region in the circuit block in which it is possible to place the capacitor. The first and second interconnect layers are to be connected to two power supply lines of respective different potentials. In the capacitance placing region, the insulation capacitance film is sandwiched between the first and second interconnect layers, on the circuit block, in order to constitute a bypass capacitor. In the other regions of the semiconductor integrated circuit device, the first and second interconnect layers are directly layered (stacked) together to constitute an interconnection of the polycide configuration. If, in this known method for generating a pattern for a semiconductor integrated circuit device, it is found in the verifying step that a capacitor is unable to be placed in a region in question, such a region in which the capacitor may be placed is sequentially searched towards upper layers.
[Patent Document 1]
    JP Patent Kokai Publication No. JP2009-33194A (paragraph 0055)